NXP Semiconductors MPC5606S - STM Count Register (STM_CNT)

System Timer Module (STM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1223
Table 39-2. STM_CR field descriptions
39.3.2.2 STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Table 39-3. STM_CNT field descriptions
Offset 0x000 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CPS
0 0 0 0 0 0
FRZ TEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-1. STM Control Register (STM_CR)
Field Description
CPS Counter Prescaler. Selects the clock divide value for the prescaler (1–256).
0x00 Divide system clock by 1
0x01 Divide system clock by 2
...
0xFF Divide system clock by 256
FRZ Freeze. Allows the timer counter to be stopped when the MCU is stopped by a debugger.
0 STM counter continues to run in debug mode.
1 STM counter is stopped in debug mode.
TEN Timer Counter Enabled.
0 Counter is disabled.
1 Counter is enabled.
Offset 0x004 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-2. STM Count Register (STM_CNT)
Field Description
CNT Timer count value used as the time base for all channels. When enabled, the counter increments at the
rate of the system clock divided by the prescale value.