NXP Semiconductors MPC5606S - Test Mode Configuration Register (ME_TEST_MC)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 923
25.3.2.9 Test Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during Test mode. Please refer to Table 25-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
25.3.2.10 Safe Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during Safe mode. Please refer to Table 25-11 for details.
Address 0xC3FD_C024 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0
PDO
0 0
MVRON
DFLAON CFLAON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0
FMPLL1ON FMPLL0ON
FXOSCON
FIRCON
SYSCLK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 25-10. Test Mode Configuration Register (ME_TEST_MC)
Address 0xC3FD_C028 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0
PDO
0 0
MVRON
DFLAON CFLAON
W
Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0
FMPLL1ON FMPLL0ON
FXOSCON
FIRCON
SYSCLK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 25-11. Safe Mode Configuration Register (ME_SAFE_MC)