NXP Semiconductors MPC5606S - Modes of Operation Based on Sync Extraction

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
442 Freescale Semiconductor
12.8.2.5 Modes of operation based on sync extraction
12.8.2.5.1 PDI Input Data (External Sync mode)
In External sync mode the timing signals (HSYNC, VSYNC and, optionally, Date Enable) are provided
the timing pins by the external video source.
External sync mode can be used in both normal mode and 8-bit narrow mode. In the instance that external
sync and narrow mode is selected, the external signals are used, and any timing information (EAV/SAV)
embedded in the data stream is ignored.
As in Figure 12-86, PDI data enable (pdi_de) should be low during Vsync and Hsync pulse, Vsync front
porch (FP_v) and back porch (BP_v), Hsync front porch (FP_h) and back porch (BP_h). This is valid for
Data Enable mode when the PDI_DE_EN bit is set in the DCU_Mode register (i.e. mode with hsync,
vsync, data enable and pdi_clk as pin signals).
Pulse width, Front and back porch values should be picked from those programmed in DCU registers. In
order to achieve lock, it must have same value as that of TFT screen. Front porch and back porch value
can be zero. Pulse width and TFT screen size parameters cannot be zero. In case they are programmed as
zero, it might lead to malfunctioning of the validation state machine.
As in Figure 12-85 Hsync must be coming during the Vsync and V blanking period. Gap between 2 Hsync
should be same during Vsync and V Blanking as during active line period. As in Figure 12-85 Positive
Edge of the Hsync and Vsync should be aligned. As in Figure 12-85 the positive edge of the Hsync and
start of the vertical front/back porch should be aligned. Polarity of hsync and vsync are selectable.
Figure 12-85. Relation between Hsync and Vsync in external synchronization
pdi_hsync
pdi_vsync
End of last
active line
Posedge of vsync and
hsync are aligned
Start of first active line
FP_V
(vertical front porch)
Value = 2
(no of hsync)
Value = 2
(no of hsync)
Value = 2
(no of hsync)
PW_V
(vertical Pulse Width)
BP_V
(vertical Back porch)
Vertical blanking period