NXP Semiconductors MPC5606S - Modified SPI Transfer Format (MTFE = 1, CPHA = 0)

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
320 Freescale Semiconductor
11.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0)
In this modified transfer format, both the master and the slave sample later in the SCK period than in
classic SPI mode, to allow for delays in device pads and board traces. These delays become a more
significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
NOTE
For the modified transfer format to operate correctly, you must thoroughly
analyze the SPI link timing budget.
The master and the slave place data on the SOUT_x pins at the assertion of the CSx signal. After the CSx
to SCK_x delay has elapsed, the first SCK_x edge is generated. The slave samples the master SOUT_x
signal on every odd-numbered SCK_x edge. The slave also places new data on the slave SOUT_x on every
odd-numbered clock edge.
The master places its second data bit on the SOUT_x line one system clock after an odd-numbered SCK_x
edge. The point where the master samples the slave SOUT_x is selected by writing to the SMPL_PT field
in the DSPIx_MCR. Table 11-24 lists the number of system clock cycles between the active edge of
SCK_x and the master sample point for different values of the SMPL_PT bit field. The master sample point
can be delayed by one or two system clock cycles.
Table 11-24. Delayed master sample point
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK and sampling of SIN
00 0
01 1
10 2
11 Invalid value