Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 231
8.10.5.6 Measurement Duration Register (CMU_MDR)
30
FLLI
FMPLL0 Clock frequency less than low reference event
This bit is set by hardware when CK_FMPLL frequency becomes lower than LFREF value
and CK_FMPLL is on as signaled by the MC_ME. It is cleared by software by writing 1.
0 No FLL event.
1 FLL event is pending.
31
OLRI
Oscillator frequency less than RC frequency event
This bit is set by hardware when the frequency of CK_FXOSC is less than
CK_FIRC/2
RCDIV
frequency and CK_FXOSC is on as signaled by the MC_ME. It can be
cleared by software by writing 1.
0No OLR event.
1 OLR event is pending.
Address offset: 0x18 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0
MD[19:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MD[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-35. Measurement Duration Register (CMU_MDR)
Table 8-34. Measurement Duration Register (CMU_MDR) field descriptions
Field Description
12–31
MD
Measurement duration bits
This register displays the measured duration in terms of IRC clock cycles. This value is
loaded in the frequency meter down counter. When SFM bit is set to 1, down counter
starts counting.
Table 8-33. Interrupt Status Register (CMU_ISR) field descriptions (continued)
Field Description
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