Crossbar Switch (XBAR)
MPC5606S Microcontroller Reference Manual, Rev. 7
282 Freescale Semiconductor
the other master releases control of the slave port if no other higher priority master is also waiting for the
slave port.
A master access is responded to with an error if the access decodes to a location not occupied by a slave
port. This is the only time the XBAR directly responds with an error response. All other error responses
received by the master are the result of error responses on the slave ports being passed through the XBAR.
10.6.4 Slave ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are
actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless
absolutely necessary.
There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively
making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from
the slave port. A requesting master which does not own the slave port is granted access after a one clock
delay.
10.6.5 Priority assignment
Each master port is assigned a fixed 3-bit priority level (hard-wired priority). The following table shows
the priority levels assigned to each master (the lowest has highest priority).
10.6.6 Arbitration
XBAR supports only a fixed-priority comparison algorithm.
10.6.6.1 Fixed priority operation
When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the
XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the
selected priority register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new requesting
master’s priority level is higher than that of the master that currently has control over the slave port (if any).
The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has
control of the slave port.
Table 10-1. Hardwired bus master priorities
Module
Port
Priority
level
Type Number
e200z0h core–CPU instructions Master 0 7
e200z0h core–CPU data / Nexus Master 0 6
eDMA Master 2 5
Display Control Unit Master 3 4
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