Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
528 Freescale Semiconductor
16.4.2.6 Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as
configuration control for miscellaneous device-level modules. The contents of this register are output from
the ECSM to other modules where the user-defined control functions are implemented. See Figure 16-6
and Table 16-7 for the Miscellaneous User-Defined Control Register definition.
Table 16-6. Miscellaneous Interrupt (MIR) field descriptions
Name Description
0
FB0AI
Flash Bank 0 Abort Interrupt
0 A flash memory bank 0 abort has not occurred.
1 A flash memory bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit.
Writing a 0 has no effect.
1
FB0SI
Flash Bank 0 Stall Interrupt
0 A flash memory bank 0 stall has not occurred.
1 A flash memory bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit.
Writing a 0 has no effect.
2
FB1AI
Flash Bank 1 Abort Interrupt
0 A flash memory bank 1 abort has not occurred.
1 A flash memory bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit.
Writing a 0 has no effect.
3
FB1SI
Flash Bank 1 Stall Interrupt
0 A flash memory bank 1 stall has not occurred.
1 A flash memory bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit.
Writing a 0 has no effect.
Address: Base + 0x0024 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MUDCR[0:15]
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MUDCR[16:31]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-6. Miscellaneous User-Defined Control Register (MUDCR)
Table 16-7. Miscellaneous User-Defined Control Register (MUDCR) field descriptions
Name Description
MUDCR User-Defined Control Register
0 The control associated with this MUDCR bit is disabled.
1 The control associated with this MUDCR bit is enabled.