NXP Semiconductors MPC5606S - System Integration Unit (SIU)

Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
56 Freescale Semiconductor
• Legacy mode allowing QuadSPI to be used as a standard DSPI (no DSI or CSI mode)
1.5.8 System Integration Unit (SIU)
The SIU controls MCU, pad configuration, external interrupt, general purpose I/O (GPIO) and internal
peripheral multiplexing.
The GPIO features the following:
• As many as four levels of internal pin multiplexing, allowing exceptional flexibility in the
allocation of device functions for each package
• Centralized general purpose input output (GPIO) control of as many as 132 input/output pins
(package dependent)
• All GPIO pins can be independently configured to support pullup, pulldown, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit-wide ports
• All peripheral pins can be alternatively configured as both general purpose input or output pins,
except ADC channels which support alternative configuration as general purpose inputs
• Direct readback of the pin value supported on all digital output pins through the SIU
• Configurable digital input filter that can be applied to as many as 14 general purpose input pins for
noise elimination on external interrupts
• Register configuration protected against change with soft lock for temporary guard or hard lock to
prevent modification until next reset
1.5.9 Flash memory
The MPC5606S microcontroller has the following flash memory features:
• As nuch as 1 MB of burst flash memory
— Typical flash memory access time: 0 wait state for buffer hits, 2 wait states for page buffer miss
at 64 MHz
—Two 4128-bit page buffers with programmable prefetch control
– One set of page buffers can be allocated for code-only, fixed partitions of code and data, all
available for any access
– One set of page buffers allocated to Display Controller Unit and the eDMA
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
—64 KB data flash memory — separate 416 KB flash block for EEPROM emulation with
prefetch buffer and 128-bit data access port
• Small block flash memory arrangement to support features such as boot block, operating system
block
• Hardware-managed flash memory writes, erases and verify sequences
• Censorship protection scheme to prevent flash memory content visibility
• Separate dedicated 64 KB data flash memory for EEPROM emulation
— Four erase sectors each containing 16 KB of memory