NXP Semiconductors MPC5606S - RX Buffer Status Register (QSPI_RBSR)

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1021
30.4.3.14 RX Buffer Status Register (QSPI_RBSR)
This register contains information related to the receive data buffer.
Address: QSPI_BASE + 0x108 Write: Disabled mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0
FSDLY
FSPHS
0 0
HSDLY
HSPHS HSENA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-13. Sampling Register (QSPI_SMPR)
Table 30-26. QSPI_SMPR field descriptions
Field Description
FSDLY Full Speed Delay selection. Select the delay with respect to the reference edge for the sample point
valid for full speed commands:
0: One clock cycle delay
1: Two clock cycles delay
FSPHS Full Speed Phase selection. Select the edge of the sampling clock valid for full speed commands:
0: Select sampling at non-inverted clock
1: Select sampling at inverted clock
HSDLY Half Speed Delay selection. Only relevant when HSENA bit is set. Select the delay with respect to
the reference edge for the sample point valid for half speed commands:
0: One clock cycle delay
1: Two clock cycles delay
HSPHS Half Speed Phase selection. Only relevant when HSENA bit is set. Select the edge of the sampling
clock valid for half speed commands:
0: Select sampling at non-inverted clock
1: Select sampling at inverted clock
HSENA Half Speed serial flash clock Enable:
This bit enables the divide by 2 of the clock to the external serial flash device for specific commands.
Refer to Section 30.7.2, Serial Flash Clock Frequency Limitations, for details.
0: Disable divide by 2 of serial flash clock for half speed commands
1: Enable divide by 2 of serial flash clock for half speed commands