Static RAM (SRAM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1108 Freescale Semiconductor
executing 32-bit write operations prior any read accesses. This is also true for implicit read accesses caused
by any write accesses of less than 32-bit as discussed in Section 33.6, SRAM ECC mechanism.
33.8 Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. All writes must
specify an even number of registers performed on 32-bit word-aligned boundaries. If the write is not the
entire 32 bits (8 or 16 bits), a read / modify / write operation is generated that checks the ECC value upon
the read.
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