Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 939
This mode can be used to stop all clock sources, thus preserving the device status. When exiting the Stop
mode, the fast internal RC oscillator (16MHz) clock is selected as the system clock until the target clock
is available.
All power domains except power domains #0 and #1 are configurable in this mode in order to reduce
leakage consumption. Active power domains are determined by the power configuration register
PCU_PCONF2 of the MC_PCU.
NOTE
If Halt is configured with ME_STOP_MC[MVRON] = 0,
ME_STOP_MC[FIRCON] = 0, and
ME_STOP_MC[SYSCLK] = 0010/0011, the Main VREG will
nevertheless remain enabled during the Stop mode if the previous Run[0..3]
mode is configured with ME_RUN[0..3]_MC[FXOSCON] = 1.
25.4.2.8 Standby mode
The device enters this mode on the following events:
• From the DRUN or one of the Run0…3 modes when the TARGET_MODE bit field of the
ME_MCTL register is written with “1101”.
As soon as any of the above events occur, a Standby mode transition request is generated. The mode
configuration information for this mode is provided by the ME_STANDBY_MC register. In this mode, the
power supply is turned off for most of the device. By default the only parts of the device that are still
powered during this mode are pads mapped on wakeup lines and power domain #0 which contains the
MC_RGM, MC_PCU, WKPU, 8K RAM, RTC_API, CANSampler, SIRC, FIRC, LCD, and device and
user option bits. The FIRC can be optionally switched off. This is the lowest power consumption mode
possible on the device.
This mode is intended as an extreme low-power mode with
• The core, the flashes, and almost all peripherals and memories powered down
and to be used by software
• To wait until it is required to do something with no need to react quickly (i.e. allow for system
startup and system clock source to be re-started)
The exit sequence of this mode is similar to the reset sequence. If there is a Standby mode request while
any wakeup event is active, the device mode does not change.
All power domains except power domain #0 are configurable in this mode in order to reduce leakage
consumption. Active power domains are determined by the power configuration register PCU_PCONF2
of the MC_PCU.
25.4.3 Mode transition process
The process of mode transition follows the following steps in a pre-defined manner depending on the
current device mode and the requested target mode. In many cases of mode transition, not all steps need
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