NXP Semiconductors MPC5606S - Device Specific Information

Real-Time Clock (RTC/API)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1097
Figure 32-2. Clock gating for RTC clocks
32.3 Device specific information
For this device:
• FXOSC, SXOSC, FIRC and SIRC clocks are provided as counter clocks for the RTC. Default
clock on reset is SIRC divided by 4.
• The RTC will be reset on destructive reset, with the exception of software watchdog reset.
• The RTC provides a configurable divider by 512 to be optionally used when FXOSC source is
selected.
32.4 Modes of operation
There are two functional modes of operation for the RTC: normal operation and low-power mode. In
normal operation, all RTC registers can read or written and the input isolation is disabled. The RTC/API
and associated interrupts are optionally enabled. In low-power mode, the bus interface is disabled and the
input isolation is enabled. The RTC/API is enabled if enabled prior to entry into low-power mode.
32-bit counter
CELL
C.G.
en
128 kHz SIRC
(cnten & clksel== 2’b00)
CELL
en
32 KHz SXOSC
(cnten & clksel== 2’b01)
CELL
en
16 MHz FIRC
(cnten & clksel== 2’b10)
CELL
C.G.
en
4-16 MHz FXOSC
(cnten & clksel== 2’b11)
C.G.
C.G.
0 1
2
CLKSEL[0:1]
3
CELL
C.G.
en
1
0
div 512
CELL
C.G.
en
1
0
div 32
div512en
div32en
CNTEN