NXP Semiconductors MPC5606S - Detailed Signal Descriptions

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 337
Figure 12-2. External signals
12.2.2 Detailed signal descriptions
Table 12-1. Detailed signal descriptions
Signal Direction Description
Parallel Data Interface (Camera Interface)
pdi_clk IN Clock for the parallel data from the input video data
pdi_vsync IN Vertical sync to indicate the start of new frame for the display
pdi_hsync IN Horizontal sync to indicate the start of new line for the display
pdi_de IN Data Enable for the camera data input
pdi_datain[17:0] IN 18-bit parallel input data for the display
Display Interface
pix_clk_out OUT Pixel clock used to drive the display panel
dcu_vsync OUT Vertical sync signal, indicating the beginning of a new frame
dcu_hsync OUT Horizontal sync signal, indicating the beginning of a new line
dcu_csync OUT Composite Sync Signal, combining horizontal and vertical sync signals to form
a composite sync signal. It includes both the HSYNC pulse and the VSYNC
pulse.
Note: Not used on this device.
dcu_tag OUT When high, this signal indicates that the pixel is tagged and an application can
calculate CRC externally on this pixel.
dcu_de OUT Data Enable. Qualifies the data output (dcu_ld)
dcu_r[7:0],
dcu_g[7:0],
dcu_b[7:0]
OUT Red, green and blue data output.
DCU Top Level
Parallel Data Interface Display Interface
pdi_clk
pix_clk_out
dcu_vsync
dcu_hsync
dcu_csync
dcu_de
dcu_r[7:0], dcu_g[7:0], dcu_b[7:0]
pdi _ datain[17:0]
pdi
_ vsync
pdi_ hsync
pdi_ de
dcu_tag