NXP Semiconductors MPC5606S - Modes of Operation

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
192 Freescale Semiconductor
• Guarantees glitchless clock transitions when changing the system clock selection
• Supports 8-, 16-, and 32-bit wide read/write accesses
8.4.1.3 Modes of operation
This section describes the basic functional modes of the MC_CGM.
8.4.1.3.1 Normal and reset modes of operation
During normal and reset modes of operation, the clock selection for the system clock is controlled by the
MC_ME.
8.4.2 External signal description
The MC_CGM delivers an output clock to the PH[4] pin for off-chip use and/or observation.
8.4.3 Memory map and register definition
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
• Not change register content
• Cause a transfer error
Table 8-2. MC_CGM register description
Address Name Description Size Access
0xC3FE_0370 CGM_OC_EN Output Clock Enable word read/write
0xC3FE_0374 CGM_OCDS_SC Output Clock Division Select byte read/write
0xC3FE_0378 CGM_SC_SS System Clock Select Status byte read
0xC3FE_037C CGM_SC_DC0 System Clock Divider Configuration 0 byte read/write
0xC3FE_037D CGM_SC_DC1 System Clock Divider Configuration 1 byte read/write
0xC3FE_037E CGM_SC_DC2 System Clock Divider Configuration 2 byte read/write
0xC3FE_0380 CGM_AC0_SC Aux Clock 0 Select Control word read/write
0xC3FE_0388 CGM_AC1_SC Aux Clock 1 Select Control word read/write
0xC3FE_038C CGM_AC1_DC0 Aux Clock 1 Divider Configuration 0 byte read/write
0xC3FE_0398 CGM_AC2_SC Aux Clock 2 Select Control word read/write
0xC3FE_0394 CGM_AC2_DC0 Aux Clock 2 Divider Configuration 0 byte read/write
0xC3FE_0398 CGM_AC3_SC Aux Clock 3 Select Control word read/write