Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
946 Freescale Semiconductor
• I/O pads power sequence driver is switched off if the target mode is one of Safe, Test, or Stop
modes
In Standby mode, the power sequence driver and all pads except the external reset and those mapped on
wakeup lines are not powered and therefore high impedance. The wakeup line configuration remains
unchanged.
This step is executed only after the Peripheral Clocks Disable process is completed.
25.4.3.18 FMPLL0 Switch-Off
Based on the FMPLL0ON bit of the ME_<current mode>_MC and ME_<target mode>_MC registers, if
FMPLL0 is to be switched off, the MC_ME requests the FMPLL0 to power down and updates its
availability status bit S_FMPLL0 of the ME_GS register to 0. This step is executed only after the System
clock switching process is completed.
25.4.3.19 Clock Sources Switch-Off
Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given
clock source is to be switched off, the MC_ME requests the clock source to power down and updates its
availability status bit S_<clock source> of the ME_GS register to 0.
This step is executed only after
• System clock switching process is completed in order not to lose the current system clock during
mode transition.
• FMPLL0 Switch-Off as the input reference clock of the FMPLL0 can be among these clock
sources. This is needed to prevent an unwanted lock transition when the FMPLL0 is switched on.
25.4.3.20 Flash Switch-Off
Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if any of the flash modules is to be put in a low-power state, the
MC_ME requests the flash to enter the corresponding low-power state and waits for the deassertion of
flash ready status signal. The exact low-power mode status of the flash modules is updated in the S_CFLA
and S_DFLA bit fields of the ME_GS register. This step is executed only when Processor and system
memory clock disable process is completed.
25.4.3.21 Main Voltage Regulator Switch-Off
Based on the MVRON bit of the ME_<current mode>_MC and ME_<target mode>_MC registers, if the
main voltage regulator is to be switched off, the MC_ME requests it to power down and clears the
availability status bit S_MVR of the ME_GS register.
This step is required only during the entry of low-power modes like Halt and Stop. This step is executed
only after completing the following processes:
• FMPLL0 Switch-Off
• Flash Switch-Off
To Next Page
Loading...
