Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
758 Freescale Semiconductor
21.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR)
0110 Priority 6
0101 Priority 5
0100 Priority 4
0011 Priority 3
0010 Priority 2
0001 Priority 1
0000 Priority 0—lowest priority
Offset: 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
VTBA (most significant 16 bits)
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA
(least significant five bits)
INTVEC
1
0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a 0.
VTBA is narrowed to 20 bits in width.
Figure 21-4. INTC Interrupt Acknowledge Register (INTC_IACKR)
Table 21-6. INTC_IACKR field descriptions
Field Description
0–20
or
0–19
VTBA
Vector Table Base Address. Can be the base address of a vector table of addresses of ISRs. The
VTBA only uses the leftmost 20 bits when the VTES bit in INTC_MCR is asserted.
21–29
or
20–28
INTVEC
Interrupt Vector.It is the vector of the peripheral or software configurable interrupt request that
caused the interrupt request to the processor. When the interrupt request to the processor asserts,
the INTVEC is updated, whether the INTC is in software or hardware vector mode.
Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28.
VTBA is then shortened by one bit to bits 0–19.
Table 21-5. PRI Values (continued)
PRI Meaning
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