Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
404 Freescale Semiconductor
Therefore, any compatible graphic stored anywhere on-chip or in an accessible interface can be displayed
on the connected TFT LCD panel with no further intervention from the CPU, except to program the DCU
to fetch and place it. The DCU also includes a dedicated memory to store the graphic for its cursor layer.
12.4.2 TFT LCD panel configuration
The nature and timing of the signals required by TFT LCD panels vary greatly between manufacturers.
Therefore, the DCU allows highly flexible and detailed configuration of these signals.
Timing diagrams for TFT LCD panels are typically divided into a horizontal timing chart and a vertical
timing chart. See Figure 12-56 for details.
Figure 12-56. HSYNC and VSYNC timing diagram
The number of pixel data slots in the horizontal timing diagram is defined by the width of the panel. The
number of line data slots is defined by the height of the panel. Both of these values are defined in the
DISP_SIZE register (DELTA_X, DELTA_Y). The width of the panel must always be defined as a multiple
of 16.
pix_clk
pixel
data
invalid data
12
3
4
delta x
invalid data
PW_H
BP_H FP_H
DELTA_X
hsync
data
Enable
hsync
invalid data invalid data
1
2
3
4
delta y
BP_V
PW_V
FP_V
line
data
vsync
data
Enable
1/RR where RR is the frame refresh rate
DELTA_X is the horizontal resolution of the display
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