Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
750 Freescale Semiconductor
20.6.2 DMA application information
The DMA interface on the I2I
2
CC is not completely autonomous and requires intervention from the CPU
to start and to terminate the frame transfer. DMA mode is only valid for Master transmit and Master receive
modes. Software must ensure that the IBCR[DMAEN] bit is not set when the I
2
C module is configured in
Master mode.
The DMA controller must only transfer one byte of data per Tx/Rx request. This is because there is no
FIFO on the I
2
C block.
The CPU should also keep the I
2
C interrupt enabled during a DMA transfer to detect the arbitration lost
condition and take action to recover from this situation. The IBCR[DMAEN] bit works as a disable for the
transfer complete interrupt. This means that during normal transfers (no errors) there will always be either
an interrupt or a request to the DMA controller, depending on the setting of the DMAEN bit. All error
conditions will trigger an interrupt and require CPU intervention. The address match condition will not
occur in DMA mode as the I
2
C should never be configured for slave operation.
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