NXP Semiconductors MPC5606S - Interrupt Registers

Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 147
5.4.3 Interrupt registers
5.4.3.1 Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) contains interrupt status bits for the ADC.
29–31
ADCSTATUS[0:2]
The value of this parameter depends on ADC status:
000 Idle
001 Power-down
010 Wait state
011 —
100 Sample
101 —
110 Conversion
111 —
Address: Base + 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 JEOC JECH EOC ECH
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-7. Interrupt Status Register (ISR)
Table 5-9. ISR field descriptions
Field Description
0–24 Reserved
A write of any value has no effect. The read value is always 0.
25–26 Reserved
A write of any value has no effect. The read value is always 0.
27 Reserved
A write of any value has no effect. The read value is always 0.
28
JEOC
End of Injected Channel Conversion interrupt (JEOC) flag
It is the interrupt of the digital end of conversion for the injected channel; active when set. When this bit
is set, a JEOC interrupt has occurred.
Table 5-8. MSR field descriptions (continued)
Field Description