NXP Semiconductors MPC5606S - Register Description

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 291
11.7.2 Register description
11.7.2.1 DSPI Module Configuration Register (DSPIx_MCR)
The DSPIx_MCR contains bits which configure attributes of the DSPI operation. The values of the HALT
and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT
and MDIS bits in the DSPIx_MCR are the only bit values that software can change while the DSPI is
running.
Table 11-3 describes the fields in the DSPI module configuration register.
Address: Base + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MSTR CONT
_SCKE
DCONF FRZ
MTFE
0
ROOE
0 0
PCSIS5 PCSIS4 PCSIS3 PCSIS2 PCSIS1 PCSIS0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
MDIS
DIS_TXF
DIS_RXF
CLR
_
TXF
CLR
_RX
F
SMPL_PT
0 0 0 0 0 0
PES
HALT
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 11-3. DSPI Module Configuration Register (DSPIx_MCR)
Table 11-3. DSPIx_MCR field descriptions
Field Description
0
MSTR
Master/Slave mode select. Configures the DSPI for Master mode or Slave mode.
0 DSPI is in Slave mode
1 DSPI is in Master mode
1
CONT_SCKE
Continuous SCK enable. Enables the serial communication clock (SCK) to run continuously. Refer
to Section 11.8.6, Continuous serial communications clock, for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
2–3
DCONF
[0:1]
DSPI Configuration. The DCONF field selects between the different configurations of the DSPI.
00 SPI.
01 Reserved
10 Reserved
11 Reserved
4
FRZ
Freeze. Enables the DSPI transfers to be stopped on the next frame boundary when the device
enters debug mode.
0 Do not halt serial transfers
1 Halt serial transfers
5
MTFE
Modified timing format enable. Enables a modified transfer format to be used. Refer to
Section 11.8.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1), for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled