NXP Semiconductors MPC5606S - Page 294

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
292 Freescale Semiconductor
6 Reserved. This bit is writable, but has no effect.
7
ROOE
Receive FIFO overflow overwrite enable. Enables an RX FIFO overflow condition to ignore the
incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is received, the
data from the transfer that generated the overflow is ignored or put in the shift register.
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the
incoming data is ignored. Refer to Section 11.8.7.6, Receive FIFO overflow interrupt request
(RFOF), for more information.
0 Incoming data is ignored
1 Incoming data is put in the shift register
8–9 Reserved, but implemented. These bits are writable, but have no effect.
10–15
PCSISn
Peripheral chip select inactive state. Determines the inactive state of the CS0_x signal. CS0_x must
be configured as inactive high for Slave mode operation.
0 The inactive state of CS0_x is low
1 The inactive state of CS0_x is high
16 Reserved.
17
MDIS
Module disable. Allows the clock to the non-memory mapped logic in the DSPI to stop, effectively
putting the DSPI in a software-controlled power-saving state. Refer to Section 11.8.8, Power-saving
features, for more information. The reset value of the MDIS bit is parameterized, with a default reset
value of 0.
0 Enable DSPI clocks
1 Allow external logic to disable DSPI clocks
18
DIS_TXF
Disable transmit FIFO. Enables and disables the TX FIFO. When the TX FIFO is disabled, the
transmit part of the DSPI operates as a simplified double-buffered SPI. Refer to Section 11.8.3.3,
FIFO disable operation, for details.
0 TX FIFO is enabled
1 TX FIFO is disabled
19
DIS_RXF
Disable receive FIFO. Enables and disables the RX FIFO. When the RX FIFO is disabled, the
receive part of the DSPI operates as a simplified double-buffered SPI. Refer to
Section 11.8.3.3,
FIFO disable operation, for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
20
CLR_TXF
Clear TX FIFO. Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter.
The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO counter
1 Clear the TX FIFO counter
21
CLR_RXF
Clear RX FIFO. Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The
CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO counter
1 Clear the RX FIFO counter
22–23
SMPL_
PT
[0:1]
Sample Point. SMPL_PT field controls when the DSPI master samples SIN in Modified Transfer
Format. Figure 11-14 shows where the master can sample the SIN pin.
00 DSPI samples SIN at driving SCK edge.
01 DSPI samples SIN one system clock after driving SCK edge.
10 DSPI samples SIN two system clocks after driving SCK edge.
11 Reserved.
Table 11-3. DSPIx_MCR field descriptions (continued)
Field Description