Boot Assist Module (BAM)
MPC5606S Microcontroller Reference Manual, Rev. 7
178 Freescale Semiconductor
6.6 Protocol
Table 6-8 summarizes the protocol and BAM action during this boot mode. All data are transmitted byte
wise.
6.6.1 Flash memory password swapping
When the chip uses the BAM to boot using FlexCAN or UART, the required flash memory password is
different depending on whether the flash memory is secured or unsecured. This difference affects how you
must program the NVPWD0, NVPWD1, NVSCI0, and NVSCI1 registers.
Table 6-8. FlexCAN Boot mode download protocol (autobaud disabled)
Protocol
step
Host sent
message
BAM response
message
Action
1 CAN ID 0x011+
64-bit password
CAN ID 0x001+
64-bit password
Password checked for validity and compared against stored
password.
2 CAN ID 0x012+
32-bit store
address+
VLE bit+
31-bit number of
bytes
CAN ID 0x002+
32-bit store
address+
VLE bit+
31-bit number of
bytes
Load address is stored for future use.
Size of download is stored for future use.
Verify if VLE bit is set to 1.
3 CAN ID 0x013+
8 to 64 bits of raw
binary data
CAN ID 0x003+
8 to 64 bits of raw
binary data
8-bit data are packed into 32-bit words. These words are saved
in SRAM starting from the “Load address”.
“Load address” increments until the number of data received
and stored matches the size as specified in the previous step.
5 None None Branch to downloaded code.
Note: Once the BAM has downloaded the code, it attempts to
disable the FlexCAN module. If there is continuing traffic
on the CAN bus from the boot master or other nodes,
then the FlexCAN module cannot be disabled and the
BAM will stall. This will prevent the downloaded code
from executing and a reset will be required to recover the
MCU.
Table 6-9. System clock frequency related to external clock frequency
f
osc
[MHz] f
rc
/f
osc
1
1
These values and consequently the f
sys
suffer from the precision of the RC internal oscillator used to
measure f
osc
through the CMU module.
f
sys
[MHz]
4–8 4–2 16–32
8–12 2–4/3 32–48
12–16 4/3–1 36–48
16–24 1–2/3 32–48
> 24 < 2/3 > 24