NXP Semiconductors MPC5606S - Initialization;Application Information

IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
728 Freescale Semiconductor
19.10 Initialization/application information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS.
2. Load the appropriate instruction for the test or action to be performed.
010 0111 Data Value Compare 2 (DVC2)
010 1000–010 1111 Reserved
011 0000 Debug Status Register (DBSR)
011 0001 Debug Control Register 0 (DBCR0)
011 0010 Debug Control Register 1 (DBCR1)
011 0011 Debug Control Register 2 (DBCR2)
011 0100–101 1111 Reserved (do not access)
110 1111 Reserved (do not access)
111 0000–111 1001 General Purpose Register Selects [0:9]
111 1010–111 1011 Reserved
111 1100 Nexus2+ Access
111 1101 LSRL Select
(factory test use only)
111 1110 Enable_OnCE
111 1111 Bypass
Table 19-6. e200z0 OnCE register addressing (continued)
RS[0:6] Register Selected