Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 213
Note: OSC_CTL register is writable only in supervisor mode.
8.7 SIRC digital interface
8.7.1 Introduction
The SIRC digital interface controls the internal low-power 128 kHz RC oscillator (SIRC). It holds control
and status registers that are accessible by software.
8.7.2 Low-Power RC Oscillator (128 kHz)
The low-power RC oscillator provides a low frequency (f
LPRC
) clock in the range of tens of kHz, requiring
less current consumption. This clock can be used as a reference clock when a fixed base time is required
for specific modules.
The low-power RC oscillator is always on in all device modes.
The SIRC clock can be further divided by a configurable division factor in the range 1 to 32 to generate
the divided clock to match system requirements. This division factor is specified by the LPRCDIV[4:0]
bits of the LPRC_CTL register.
The SIRC oscillator output frequency can be trimmed by the LPRCTRIM[4:0] bits of the LPRC_CTL
register. These bits can be programmed to modify an internal capacitor/resistor. After power-on reset, the
trimming bits are provided by the flash options. After the first write access, only the value specified by the
LPRCTRIM[4:0] bits will control the trimming.
30
S_OSC
Crystal oscillator status
0 Crystal oscillator output clock is not stable.
1 Crystal oscillator is providing a stable clock.
31
OSCON
Crystal oscillator powerdown control
0 Crystal oscillator is switched off.
1 Crystal oscillator is switched on.
Table 8-17. Crystal Oscillator Control Register (OSC_CTL) field descriptions (continued)
Field Description
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