NXP Semiconductors MPC5606S - C.3 Changes between Revisions 4 and 5

Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1329
C.3 Changes between revisions 4 and 5
Table C-3. Changes between revisions 4 and 5
Chapter Description
Throughout Editorial changes and improvements.
Overview In the “MPC5606S family device comparison” table:
• Changed “32 kHz slow external crystal oscillator” to “32 KHz slow external crystal
oscillator”.
• Revised the entry for “LCD driver”.
Added the feature details.
Added the “How to use the MPC5606S documents” section.
Added the “Using the MPC5606S” section.
Memory Map Revised the SRAM entries.
Signal Description In the “Voltage supply pin descriptions” table, revised the entry for VDD12.
In the “Pad types” section, changed “registers in the device reference manual” to “registers
in the SIUL chapter of the device reference manual”.
Renamed the “Functional ports” section.
In the “Pad type description” table:
• Added a footnote.
• Revised the entry for SMD.
Safety Revised the Overview section.
Deleted the text referring to device-specific reset values (all correct values for the device
are shown in the register figures).
In the SWT section, revised the “Functional description” section.
Analog-to-Digital
Converter
In the “Max AD_clk frequency and related configuration settings” table, changed the
INPSAMP value associated with AD_clk f
max
= 32 + 4% (was 6h, is 7h).
Clock Description Replaced QSPI with QuadSPI.
In the “Clock architecture” section, changed “32 kHz” to “32 KHz”.
Revised the “Auxiliary clocks” section.
Revised the “Clock gating” section.
In the CGM_SC_DC0...2 section, added “The divided clock is the reference for the
associated peripheral set” to the description.
Revised the ‘System clock dividers” section.
Revised the “Auxiliary clock dividers” section.
Configurable
Enhanced Modular IO
Subsystem
In the “Register description” section, changed “and 24-bit wide data registers” to “and 16-bit
wide data registers”.
In the “Modulus Counter Buffered (MCB) mode” section, changed “which is $ff_ffff for a
24-bit counter” to “which is 0xFFFF for a 16-bit counter”.
In the “Output Pulse Width and Frequency Modulation Buffered (OPWFMB) mode” section,
changed “which is $ff_ffff for a 24-bit counter” to “which is 0xFFFF for a 16-bit counter”.
In the “REDC block diagram” figure, changed “24-bit wide” to “16-bit wide”.
Crossbar Switch In the “XBAR block diagram” figure, changed QSPI to QuadSPI.
Deleted the “XBAR Switch Ports” table.
Display Control Unit In the “Layer configuration and blending” section, revised the blending-algorithm equations.
DMA Channel Mux Revised the Overview and Features sections.
Error Correction Status
Module
Revised the memory map to show correct sizes for PCT and REV.
Deleted the IMC register (not available on this device).