Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1328 Freescale Semiconductor
Nexus Development
Interface (NDI)
In the MCKO_DIV bit field description of the “DC1 field descriptions” table, added NOTE:
“If the Nexus clock divider (NPC_PCR[MCKO_DIV]) is set to 8 and the Nexus clock
gating control (NPC_PCR[MCKO_GT]) is enabled, the Nexus clock (MCKO) will be
disabled prior to the completion of transmission of the Nexus message data. Do not
enable the automatic clock gating mode when the Nexus clock divider is set to 8.”
(ERR002161)
In the “Read/Write Access Control/Status (RWCS” section, added sentence: “Writes to this
register do not begin until one JTAG clock (TCK) cycle after leaving the JTAG Update-DR
state.” (ERR00817)
Quad Serial Peripheral
Interface (QuadSPI)
Added NOTE: below “Connectivity of signals on this device” table (ERR003005)
Reset Generation
Module (MC_RGM)
In “Functional Event Status Register (RGM_FES)” section, added NOTE: “Clearing each
flag in this register requires two clock cycles because of a synchronization mechanism.
As a consequence if a reset occurs while clearing is on-going the reset may interrupt the
clearing mechanism leaving the flag set.” (ERR002958)
In “Functional Event Status Register (RGM_FES) field descriptions” table, changed 10
instances of “destructive reset assertion” to “power-on reset.”
In “Destructive Event Status Register (RGM_DES)” section, added NOTE: “Clearing each
flag in this register requires two clock cycles because of a synchronization mechanism.
As a consequence if a reset occurs while clearing is on-going the reset may interrupt the
clearing mechanism leaving the flag set.” (ERR002958)
In “Functional Bidirectional Reset Enable Register (RGM_FBRE)” section, added NOTE: “It
is not possible for a functional event to perform a short reset sequence and also assert
the external reset pin. If any functional event is defined to perform a short reset sequence
in the RGM_FESS register and also assert the external reset pin, then it will perform a
long reset starting with PHASE3 and not assert the external reset pin.” (ERR002977,
ERR003049)
At end of “STANDBY Entry Sequence” section, added NOTE: “If the device is in STANDBY
mode and an external reset occurs, the MC_RGM may not assert the external reset for
the duration of the reset sequence even when RGM_FBRE[BE_EXR] = 0. This incorrect
behavior occurs only if the system releases the external reset before the end of reset
sequence PHASE1.” (ERR3086)
Sound Generation
Logic (SGL)
Added NOTE: below “Truth table for MODE_SEL[SOUND_CTRL]” table describing
SOUND_CTRL behavior (ERR003184)
Wakeup Unit (WKPU) Corrected abbreviation of WakeUp Unit module to WKPU.
Corrected “AIPS” to “PBRIDGE.”
Table C-2. Changes between revisions 5 and 6 (continued)
Chapter Description
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