Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
516 Freescale Semiconductor
TCD.daddr = 0x2000
TCD.doff = 4
TCD.dsize = 2
TCD.dlast_sga= -16
TCD.int_maj = 1
TCD.start = 1 (TCD.word7 should be written last after all other fields have been initialized)
All other TCD fields = 0
This generates the following sequence of events:
1. IPS write to the TCD.start bit requests channel service
2. The channel is selected by arbitration for servicing
3. DMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1
4. DMA engine reads: channel TCD data from local memory to internal register file
5. The source to destination transfers are executed as follows:
a. read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b. write_word(0x2000) first iteration of the minor loop
c. read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d. write_word(0x2004) second iteration of the minor loop
e. read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f. write_word(0x2008) third iteration of the minor loop
g. read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h. write_word(0x200c) last iteration of the minor loop major loop complete
6. DMA engine writes: TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 1 (TCD.biter)
7. DMA engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1
8. The channel retires
The DMA goes idle or services next channel.
15.5.4.2 Multiple requests
The next example is the same as the previous example, with the exception of transferring 32 bytes via two
hardware requests. The only fields that change are the major loop iteration count and the final address
offsets. The DMA is programmed for two iterations of the major loop transferring 16 bytes per iteration.
After the channel’s hardware requests is enabled in the DMAERQ register, channel service requests are
initiated by the slave device.
TCD.citer = TCD.biter .
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