NXP Semiconductors MPC5606S - Register Description

Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1125
35.3.2 Register description
This section provides detailed descriptions of all registers in ascending address order. Table 35-3 provides
a key for the register figures and register tables.
0x30 Motor Controller Duty Cycle Register 8 (MCDC8) RW, 16-bit on page 1129
0x32 Motor Controller Duty Cycle Register 9 (MCDC9) RW, 16-bit on page 1129
0x34 Motor Controller Duty Cycle Register 10 (MCDC10) RW, 16-bit on page 1129
0x36 Motor Controller Duty Cycle Register 11 (MCDC11) RW, 16-bit on page 1129
0x38 Reserved — —
0x39 Reserved — —
0x3A Reserved — —
0x3B Reserved — —
0x3C Reserved — —
0x3D Reserved — —
0x3E Reserved — —
0x3F Reserved — —
0x40 Short-circuit Detector Timeout Register (MCSDTO) RW, 8-bit on page 1131
0x41 Reserved — —
0x42 Reserved — —
0x43 Reserved — —
0x44 Short-circuit Detector Enable Register 0 (MCSDE0) RW, 8-bit on page 1131
0x45 Short-circuit Detector Enable Register 1 (MCSDE1) RW, 8-bit on page 1132
0x46 Short-circuit Detector Enable Register 2 (MCSDE2) RW, 8-bit on page 1132
0x47 Reserved — —
0x48 Short-circuit Detector Interrupt Enable Register 0 (MCSDIEN0) RW, 8-bit on page 1133
0x49 Short-circuit Detector Interrupt Enable Register 1 (MCSDIEN1) RW, 8-bit on page 1133
0x4A Short-circuit Detector Interrupt Enable Register 2 (MCSDIEN2) RW, 8-bit on page 1134
0x4B Reserved — —
0x4C Short-circuit Detector Interrupt Register 0 (MCSDI0) R/MW, 8-bit on page 1134
0x4D Short-circuit Detector Interrupt Register 1 (MCSDI1) R/MW, 8-bit on page 1135
0x4E Short-circuit Detector Interrupt Register 2 (MCSDI2) R/MW, 8-bit on page 1135
0x4F Reserved — —
Table 35-3. Register Access Conventions
Convention Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not
writeable.
FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
Table 35-2. SMC memory map (continued)
Address
offset
Use
Recommende
d
Access type
Location