NXP Semiconductors MPC5606S - DSPI Receive FIFO Registers 0-4 (Dspix_Rxfrn)

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
306 Freescale Semiconductor
Table 11-16 describes the fields in the DSPI transmit FIFO register.
11.7.2.9 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes. Each register is
an entry in the RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers
does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO:
DSPIx_RXFR0–DSPIx_RXFR3.
Address:
Base + 0x003C (DSPIx_TXFR0)
Base + 0x0040 (DSPIx_TXFR1)
Base + 0x0044 (DSPIx_TXFR2)
Base + 0x0048 (DSPIx_TXFR3)
Base + 0x004C (DSPIx_TXFR4)
Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R TXCMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-9. DSPI Transmit FIFO Register 0–4 (DSPIx_TXFRn)
Table 11-16. DSPIx_TXFRn field descriptions
Field Description
0–15
TXCMD
[0:15]
Transmit command. Contains the command that sets the transfer attributes for the SPI data. Refer to
Section 11.7.2.6, DSPI PUSH TX FIFO Register (DSPIx_PUSHR), for details on the command field.
16–31
TXDATA
[0:15]
Transmit data. Contains the SPI data to be shifted out.