NXP Semiconductors MPC5606S - Generation of Stop

Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 747
complete flag as the flag timing is dependent on a number of factors including the I
2
C bus frequency. This
bit may not conclusively provide an indication of a transfer complete situation. It is recommended that
transfer complete situations are detected using the IBIF flag.
Software may service the I
2
C I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle, the master will always be in transmit
mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR,
then the Tx/Rx bit should be toggled at this stage.
During Slave mode address cycles (IAAS=1) the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For Slave mode data
cycles (IAAS=0) the SRW bit is not valid. The Tx/Rx bit in the control register should be read to determine
the direction of the current transfer.
The following is an example software sequence for 'master transmitter' in the interrupt routine.
clear bit 1, IBSR// Clear the IBIF flag
if (bit 5, IBCR ==0)
slave_mode()// run Slave mode routine
if (bit 4, IBCR ==0))
receive_mode()// run receive_mode routine
if (bit 0, IBSR == 1)// if NO ACK
end();// end transmission
else
IBDR = data_to_transmit// transmit next byte of data
20.6.1.4 Generation of stop
A data transfer ends with a stop signal generated by the 'master' device. A master transmitter can simply
generate a stop signal after all the data has been transmitted. The following is an example showing how a
stop condition is generated by a master transmitter.
if (tx_count == 0) or// check to see if all data bytes have been transmitted
(bit 0, IBSR == 1) {// or if no ACK generated
clear bit 5, IBCR// generate stop condition
}
else {
IBDR = data_to_transmit// write byte of data to DATA register
tx_count --// decrement counter
}// return from interrupt
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)
before reading the second last byte of data. Before reading the last byte of data, a stop signal must first be
generated. The following is an example showing how a stop signal is generated by a master receiver.
rx_count --// decrease the rx counter
if (rx_count ==1)// 2nd last byte to be read ?
bit 3, IBCR = 1// disable ACK
if (rx_count == 0)// last byte to be read ?
bit 1, IBCR = 0// generate stop signal
else