Periodic Interrupt Timer (PIT)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 975
27.3.2 Register descriptions
This section describes in address order all the PIT registers and their individual bits.
27.3.2.1 PIT Module Control Register (PITMCR)
The PIT Module Control Register (PITMCR) controls whether the timer clocks should be enabled and
whether the timers should run in debug mode.
27.3.2.2 Timer Load Value (LDVAL) register
The Timer Load Value (LDVAL) register selects the timeout period for the timer interrupts.
Offset: Base + 0x000 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0
0
0 0
MDIS FRZ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Figure 27-2. PIT Module Control Register (PITMCR)
Table 27-3. PITMCR field descriptions
Field Description
MDIS Module Disable. This is used to disable the module clock. This bit should be enabled before any other
setup is done.
0 Clock for PIT Timers is enabled
1 Clock for PIT Timers is disabled (default)
FRZ Freeze. Allows the timers to be stopped when the device enters debug mode.
0 Timers continue to run in debug mode.
1 Timers are stopped in debug mode.
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