NXP Semiconductors MPC5606S - DSPI PUSH TX FIFO Register (Dspix_Pushr)

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 303
11.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
The DSPIx_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred
to the TX FIFO. Refer to Section 11.8.3.4, transmit First In First Out (TX FIFO) buffering mechanism, for
more information. Write accesses of 8 or 16 bits to the DSPIx_PUSHR transfer 32 bits to the TX FIFO.
NOTE
TXDATA is used in Master and Slave modes.
15
RFDF_DIRS
Receive FIFO drain DMA or interrupt request select. Selects between generating a DMA request or
an interrupt request. When the RFDF flag bit in the DSPIx_SR is set, and the RFDF_RE bit in the
DSPIx_RSER is set, the RFDF_DIRS bit selects between generating an interrupt request or a DMA
request.
0 Interrupt request is selected
1 DMA request is selected
16–31 Reserved.
Address: Base + 0x0034 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CON
T
CTAS EOQ
CT
CNT
0 0
0 0
0 0 0
PCS
2
PCS
1
PCS
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-7. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
Table 11-13. DSPIx_RSER field descriptions (continued)
Field Description