NXP Semiconductors MPC5606S - LIN Control Register 1 (LINCR1)

LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 837
Figure 23-6. Key to register fields
NOTE
32-bit read/write access is preferred for all LINFlex registers.16-bit and
8-bit access is possible for all registers except for BDRL and BDRM. For
these registers, 16- or 8-bit access is not permitted; they must be accessed in
32-bit mode only.
23.7.2.1 LIN control register 1 (LINCR1)
Always
reads
1
1
Always
reads
0
0
R/W
bit
BIT
Read-
only bit
BIT
Write-
only bit
Write 1
to clear
BIT
Self-
clear
bit
0
N/A
BIT w1c BIT
Address: Base + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CCD CFD LASE AWUM MBL[0:3] BF SFTM LBKM MME SBDT RBLM SLEEP INIT
W
Reset 0 0 0 0 0 0 0 0 1 0 0 * 0 0 1 0
*: This field resets to 0 for LINFlex_0 and 1 for LINFlex_1.
Figure 23-7. LIN control register 1 (LINCR1)
Table 23-3. LINCR1 field descriptions
Field Description
0:15 Reserved
CCD
16
Checksum calculation disable
This bit disables the checksum calculation (see Table 23-4).
0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only.
1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can
program this register to send a software-calculated CRC (provided CFD is 0).
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
CFD
17
Checksum field disable
This bit disables the checksum field transmission (see Tabl e 23-4).
0 Checksum field is sent after the required number of data bytes is sent.
1 No checksum field is sent.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.