LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
838 Freescale Semiconductor
LASE
18
LIN Slave Automatic Resynchronization Enable
0 Automatic resynchronization disable.
1 Automatic resynchronization enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
AWUM
19
Automatic Wake-Up Mode
This bit controls the behavior of the LINFlex hardware during Sleep mode.
0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR.
1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection. The
SLEEP bit of the LINCR is cleared by hardware whenever WUF bit in the LINSR is set.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
MBL[0:3]
20:23
LIN Master Break Length
These bits indicate the Break length in Master mode (see Tabl e 23-5).
Note: These bits can be written in Initialization mode only. They are read-only in Normal or Sleep
mode.
BF
24
Bypass filter
0 No interrupt if identifier does not match any filter.
1 An RX interrupt is generated on identifier not matching any filter.
Note:
• If no filter is activated, this bit is reserved.
• This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SFTM
25
Self-test Mode
This bit controls the Self-test mode. For more details, see Section 23.6.2, Self-test mode.
0 Self-test mode disable.
1 Self-test mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LBKM
26
Loopback Mode
This bit controls the Loopback mode. For more details see Section 23.6.1, Loopback mode.
0 Loopback mode disable.
1 Loopback mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode
MME
27
Master Mode Enable
0 Slave mode enable.
1 Master mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SBDT
28
Slave Mode Break Detection Threshold
0 11-bit break.
1 10-bit break.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
RBLM
29
Receive Buffer Locked Mode
0 Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming
message is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Table 23-3. LINCR1 field descriptions (continued)
Field Description
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