NXP Semiconductors MPC5606S - Clock Polarity Switching between DSPI Transfers

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 323
When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS
signal remains asserted for the duration of the two transfers. The delay between transfers (t
DT
) is not
inserted between the transfers.
Figure 11-19 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1.
Figure 11-19. Example of continuous transfer (CPHA = 1, CONT = 1)
In Figure 11-19, the period length at the start of the next transfer is the sum of t
ASC
and t
CSC
. It does not
include a half-clock period. The default settings for these provide a total of four system clocks. In many
situations, t
ASC
and t
CSC
must be increased if a full half-clock period is required.
When the CONT bit = 1 and the CS signals for the next transfer are different from the present transfer, the
CS signals behave as if the CONT bit was not set.
Switching CTAR registers or changing which PCS signals are asserted between frames while using
Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is
switched or different PCS signals are selected.
11.8.5.6 Clock polarity switching between DSPI transfers
If you want to switch polarity between non-continuous DSPI frames, it is important to remember that the
edge generated by the change in the idle state of the clock occurs one system clock before the assertion of
the chip select for the next frame.
NOTE
It is mandatory to fill the TX FIFO with the number of entries that will be
concatenated together under one PCS assertion for both master and slave
before the TX FIFO becomes empty. For example, while transmitting in
Master mode, it should be ensured that the last entry in the TX FIFO, after
which TX FIFO becomes empty, must have the CONT bit in command
frame as deasserted (CONT bit = 0). While operating in Slave mode, it
should be ensured that when the last entry in the TX FIFO is completely
transmitted (that is, the corresponding TCF flag is asserted and TX FIFO is
empty), the slave should be de-selected for any further serial
communication. Otherwise, an underflow error occurs.
SCK
(CPOL = 0)
CS
t
ASC
SCK
(CPOL = 1)
Master SOUT
t
CSC
t
CSC
t
CSC
= CS to SCK delay.
t
ASC
= After SCK delay.
Master SIN