NXP Semiconductors MPC5606S - DMA Performance

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 509
Figure 15-36. DMA operation, part 3
15.4.3 DMA performance
This section addresses the performance of the DMA module, focusing on two separate metrics. In the
traditional data movement context, performance is best expressed as the peak data transfer rates achieved
using the DMA. In most implementations, this transfer rate is limited by the speed of the source and
destination address spaces. In a second context where device-paced movement of single data values
to/from peripherals is dominant, a measure of the requests which can be serviced in a fixed time is a more
interesting metric. In this environment, the speed of the source and destination address spaces remains
important, but the microarchitecture of the DMA also factors significantly into the resulting metric.
The peak transfer rates for several different source and destination transfers are shown in Table 15-29. The
following assumptions apply to Table 15-29 and Table 15-30:
• Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data
phase
j
j+1
n-1
SRAM
Transfer
Control
Descriptor (TCD)
DMA engine
addr_path
data_path
DMA
IPS
Bus
AMBA
Bus
ipd_req[n-1:0]
dma_ipi_int[n-1:0]
0
c
o
n
t
r
o
l
pmodel_charb
addr
wdata[31:0]
rdata[31:0]
hrdata[{63,31}:0]
hwdata[{63,31}:0]
haddr[31:0]
dma_ipd_done[n-1:0]