NXP Semiconductors MPC5606S - Page 513

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 511
• Cycle ?+1: This cycle represents the data phase of the last destination write
• Cycle ?+2: The DMA engine completes the execution of the inner minor loop and prepares to write
back the required TCDn fields into the local memory. TCD word7 is read and checked for channel
linking or scatter/gather requests.
• Cycle ?+3: The appropriate fields in the first part of the TCDn are written back into the local
memory
• Cycle ?+4: The fields in the second part of the TCDn are written back into the local memory. This
cycle coincides with the next channel arbitration cycle start.
• Cycle ?+5: The next channel to be activated performs the read of the first part of its TCD from the
local memory. This is equivalent to Cycle 4 for the first channel’s service request.
Assuming zero wait states on the AHB system bus, DMA requests can be processed every 9 cycles.
Assuming an average of the access times associated with IPS-to-SRAM (4 cycles) and SRAM-to-IPS
(5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)2 + 3). This is the time from
Cycle 4 to Cycle “?+5”. The resulting peak request rate, as a function of the platform frequency, is shown
in Table 15-30. This metric represents millions of requests per second.
A general formula to compute the peak request rate (with overlapping requests) is:
PEAKreq = freq  [ entry + (1 + read_ws) + (1 + write_ws) + exit ] Eqn. 15-1
where:
PEAKreq—peak request rate
freq—platform frequency
entry—channel startup (4 cycles)
read_ws—wait states seen during the system bus read data phase
write_ws—wait states seen during the system bus write data phase
exit—channel shutdown (3 cycles)
For example: consider a platform with the following characteristics:
Table 15-30. DMA peak request rate [MReq/sec]
Platform Speed
Request Rate
(zero wait state)
Request Rate
(with wait states)
66.6 MHz 7.4 5.8
83.3 MHz 9.2 7.2
100.0 MHz 11.1 8.7
133.3 MHz 14.8 11.6
150.0 MHz 16.6 13.0