Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 595
• Sector Erase
• Single Bank: Read-While-Modify not available
• Erase Suspend available (Program Suspend not available)
• Software programmable Program/Erase Protection to avoid unwanted writings
• Censored mode against piracy
• Not usable as main Code Memory
• Shadow block not available
• “OTP” area in Test flash block
17.3.3 Block diagram
The flash memory macrocell contains one matrix module, composed of a single bank: Bank 0, normally
used for Code storage. No Read-While-Modify operations are possible.
The Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands
to the FPEC are given through a user registers Interface.
The read data bus is 128 bits wide, while the flash memory registers are on a separate 32-bit bus.
The high voltages needed for Program/Erase operations are internally generated addressed in user memory
map.
Figure 17-26. Flash macrocell structure
64 KB
+ 16KB Test Flash
HV generator
Flash
Controller
Flash
Matrix
Registers
Program/Erase
Registers
Interface
Flash Bank 0
Interface
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