Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
354 Freescale Semiconductor
Figure 12-3. CtrlDescL0_1 Register
12.3.4.2 Control Descriptor L0_2 Register
Figure 12-4 represents the control descriptor L0_2 register. This register sets the origin (top/left) of the
layer associated with the register.
Offset:
0x000 (CtrlDescL0_1)
0x01C (CtrlDescL1_1)
0x038 (CtrlDescL2_1)
0x054 (CtrlDescL3_1)
0x070 (CtrlDescL4_1)
0x08C (CtrlDescL5_1)
0x098 (CtrlDescL6_1)
0x0C4 (CtrlDescL7_1)
0x0E0 (CtrlDescL8_1)
0x0FC (CtrlDescL9_1)
0x118 (CtrlDescL10_1)
0x134 (CtrlDescL11_1)
0x150 (CtrlDescL12_1)
0x16C (CtrlDescL13_1)
0x188 (CtrlDescL14_1)
0x194 (CtrlDescL15_1) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
HEIGHT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
WIDTH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-5. CtrlDescL0_1 field descriptions
Field Description
6–15
HEIGHT
Height of the layer in pixels
20–31
WIDTH
Width of the layer (in pixels). The layer width must be in multiples of the number of pixels that
can be stored in 32 bits (except for the special case of 1 bit per pixel), and therefore differs
depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width
must be configured in multiples of 16. See
Section 12.4.5.3, Layer size and positioning.
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