Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
54 Freescale Semiconductor
— QuadSPI serial flash controller
— One slave port combining:
– Flash port dedicated to the Display Control Unit and eDMA module
– Graphics SRAM
– Peripheral bridge
• 32-bit internal address bus, 32-bit internal data bus
1.5.4 Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable
channels, with minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine, that performs source and destination address calculations, and the actual data movement
operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the
channels. This implementation is utilized to minimize the overall block size. The eDMA module provides
the following features:
• 16 channels support independent 8-, 16-, or 32-bit single value or block transfers.
• Supports variable-sized queues and circular queues.
• Source and destination address registers are independently configured to post-increment or remain
constant.
• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt, or eDMA channel request.
• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer.
• DMA transfers possible between system memories, QuadSPI, DSPIs, I
2
C, ADC, eMIOS, and
General Purpose I/Os (GPIOs).
• Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA
channel with as many as 64 potential request sources.
1.5.5 Inter-IC communications module (I
2
C)
The I
2
C module features the following:
• As many as four I
2
C modules supported
• Two-wire bi-directional serial bus for on-board communications
• Compatibility with I
2
C bus standard
• Multimaster operation
• Software-programmable for one of 256 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
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