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NXP Semiconductors MPC5606S - RAM ECC Master Number Register (REMR)

NXP Semiconductors MPC5606S
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Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
540 Freescale Semiconductor
16.4.2.17 RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the XBAR bus master number of the last properly enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes, and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT, and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-16 and Table 16-18 for the RAM ECC Master Number Register definition.
16.4.2.18 RAM ECC Attributes (REAT) register
The REAT is an 8-bit register for capturing the XBAR bus master attributes of the last properly enabled
ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event
in the RAM causes the address, attributes, and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT, and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-17 and Table 16-19 for the RAM ECC Attributes Register definition.
Address: Base + 0x0066 Access: User read-only
0 1 2 3 4 5 6 7
R 0 0 0 0 REMR[0:3]
W
Reset
1
1
Value is undefined at reset.
Figure 16-16. RAM ECC Master Number Register (REMR)
Table 16-18. RAM ECC Master Number (REMR) field descriptions
Name Description
4-7
REMR[0:3]
RAM ECC Master Number Register
This 4-bit register contains the XBAR bus master number of the faulting access of the last properly
enabled RAM ECC event.
Address: Base + 0x0067 Access: User read-only
0 1 2 3 4 5 6 7
R Write Size[0:2] Protection[0:3]
W
Reset
1
1
Value is undefined at reset.
Figure 16-17. RAM ECC Attributes (REAT) Register

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