Wakeup Unit (WKPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
1242 Freescale Semiconductor
NOTE
Writing a 0 to both NREE and NFEE disables the NMI functionality
completely (i.e. no system wakeup or interrupt will be generated on any pad
activity)!
41.4.2.3 Wakeup/Interrupt Status Flag Register (WISR)
This register holds the wakeup/interrupt flags.
NOTE
Status bits associated with on-chip wakeup sources are located to the left of
the external wakeup/interrupt status bits and are read only. The wakeup for
these sources must be configured and cleared at the on-chip wakeup source.
Also, the configuration registers for the external interrupts/wakeups do not
have corresponding bits.
6
NFEE
NMI Falling-edge Events Enable
0 Falling-edge event is disabled
0 Falling-edge event is disabled
1 Falling-edge event is enabled
7
NFE
NMI Filter Enable
Enable analog glitch filter on the NMI pad input.
0 Filter is disabled
1 Filter is enabled
Address : Base + 0x0014 Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 EIF[20:0]
1
1
Not all bits are available in the 144-pin package.
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 41-4. Wakeup/Interrupt Status Flag Register (WISR)
Table 41-5. WISR field descriptions
Field Description
EIF[x] External Wakeup/Interrupt Status Flag x.
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
0 No event has occurred on the pad
1 An event as defined by WIREER and WIFEER has occurred
Table 41-4. NCR field descriptions (continued)
Field Description
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