NXP Semiconductors MPC5606S - Emios200 Disable Channel (EMIOSUCDIS)

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 245
9.4.2.4 eMIOS200 Disable Channel (EMIOSUCDIS)
The two modules on this device, EMIOS0 and EMIOS1, have different structures for this register as shown
in Figure 9-10 and Figure 9-11.
Address: eMIOS1 base address +0x08 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
OU
23
OU
22
OU
21
OU
20
OU
19
OU
18
OU
17
OU
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-9. eMIOS200 Output Update Disable Register (EMIOSOUDIS) for EMIOS1
Table 9-12. EMIOSOUDIS field descriptions
Field Description
OU[n] Channel [n] Output Update Disable bit
When running MCB or an output mode, values are written to registers A2 and B2. OU[n] bits are used
to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel.
0 Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next
period. Unless stated otherwise, transfer occurs immediately.
1 Transfers disabled
Address: eMIOS0 base address +0x0C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
CHDI
S23
CHDI
S22
CHDI
S21
CHDI
S20
CHDI
S19
CHDI
S18
CHDI
S17
CHDI
S16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CHDI
S15
CHDI
S14
CHDI
S13
CHDI
S12
CHDI
S11
CHDI
S10
CHDI
S9
CHDI
S8
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-10. eMIOS200 Enable Channel Register (EMIOSUCDIS) for EMIOS200_0