FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
710 Freescale Semiconductor
equal to one and CAN bit timing with eight time quanta per bit, the ratio between peripheral and oscillator
clock frequencies should be at least two.
18.4.9 Modes of operation: details
18.4.9.1 Freeze mode
This mode is entered by asserting the HALT bit in the MCR Register or when the MCU is stopped by a
debugger. In both cases it is also necessary that the FRZ bit be asserted in the MCR Register and the
module is not in any of the low-power modes (Disable or Stop). When Freeze mode is requested during
transmission or reception, the FlexCAN does the following:
• Waits to be in either Intermission, Passive Error, Bus Off, or Idle state
• Waits for all internal activities like arbitration, matching, move-in, and move-out to finish
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR
After requesting Freeze mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before
executing any other action—otherwise the FlexCAN may operate in an unpredictable way. In Freeze
mode, all memory-mapped registers are accessible.
Exiting Freeze mode is done in one of the following ways:
• CPU negates the FRZ bit in the MCR Register.
• The MCU is started by the debugger and/or the HALT bit is negated.
Once out of Freeze mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11 consecutive
recessive bits.
18.4.9.2 Module Disable mode
This low-power mode is entered when the MDIS bit in the MCR Register is asserted. If the module is
disabled during Freeze mode, it shuts down the clocks to the CPI and MBM submodules, sets the
LPM_ACK bit, and negates the FRZ_ACK bit. If the module is disabled during transmission or reception,
FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then
checks to see if it is recessive
• Waits for all internal activities like arbitration, matching, move-in, and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM submodules
• Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory-mapped registers, except
the Free Running Timer, the Error Counter Register, and the Message Buffers, which cannot be accessed
To Next Page
Loading...
