Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1055
If implemented, the ipg_enable_clk signal can stop the clock to the non-memory mapped logic. When
ipg_enable_clk is negated, the QuadSPI is in a dormant state, but the memory-mapped registers are still
accessible. Certain read or write operations have a different effect when the QuadSPI is in the Module
Disable mode. Clearing either of the FIFOs will not have any effect in the Module Disable mode. In the
Module Disable mode, all status bits and register flags in the QuadSPI will return the correct values when
read, but writing to them will have no effect. Writing to the QSPI_TCR during Module Disable mode will
not have any effect. Interrupt and DMA request signals cannot be cleared while in the Module Disable
mode.
It is not allowed to write to the FIFO registers in this mode.
Note that the following actions are illegal in SFM mode during the time starting with raising the request
to enter Module Disable mode and ending with leaving the Module Disable mode:
• Issue a new SFM command
• Issue a new AHB request
30.5.4.2 Leaving power-saving modes
In the Stop mode and the Module Disable mode the clocks to the QuadSPI module are switched off by
external circuitry. Note that after the QuadSPI module has left these power saving modes and has returned
to normal operation in SFM mode the execution of the first SFM command is deferred until the clock to
drive that part of the module related to the serial flash device is available. Depending from the point in
time when the first SFM command is programmed the actual execution of that command will start with a
slight delay w.r.t. the re-enabling of the clock signal.
30.5.4.3 Slave bus signal gating
The QuadSPI’s module enable signal is used to gate slave bus signals such as address, byte enable,
read/write and data. This prevents toggling slave bus signals from propagating through parts of the
QuadSPI’s combinational logic and consuming power unless it is a QuadSPI access. The module enable
signal can also be used to gate the clock (ipg_clk_s) to the memory-mapped logic.
30.6 Initialization/application information
30.6.1 How to change queues—SPI modes only
This section presents an example of how to change queues for the QuadSPI. The queues are not part of the
QuadSPI, but the QuadSPI includes features in support of queue management. Queues are supported in
both SPI modes.
1. Only the last command word from a queue is executed. The EOQ bit in the command word is set
to indicate to the QuadSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the QSPI_SPISR is set.
3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,
putting the QuadSPI in the Stopped state. The TXRXS bit is negated to indicate the Stopped state.
To Next Page
Loading...
