Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
506 Freescale Semiconductor
TCDn.{saddr, daddr, citer} back into the local memory. If the major iteration count is
exhausted, additional processing is performed, including the final address pointer updates,
reloading the TCDn.citer field, and a possible fetch of the next TCDn from memory as part of
a scatter/gather operation.
— data_path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The AMBA-AHB read data bus is the primary input, and
the AHB write data bus is the primary output.
The addr_ and data_path modules directly support the 2-stage pipelined AMBA-AHB bus. The
addr_path module represents the first stage of the bus pipeline (the address phase), while the
data_path module implements the second stage of the pipeline (the data phase).
— pmodel_charb: This module implements the first section of DMA’s programming model as
well as the channel arbitration logic. The programming model registers are connected to the
IPS bus (not shown). The ipd_req[n] inputs and dma_ipi_int[n] outputs are also connected to
this module (via the control logic).
— control: This module provides all the control functions for the DMA engine. For data transfers
where the source and destination sizes are equal, the DMA engine performs a series of source
read, destination write operations until the number of bytes specified in the inner ‘minor loop’
byte count has been moved. For descriptors where the sizes are not equal, multiple access of
the smaller size data are required for each reference of the larger size. As an example, if the
source size references 16-bit data and the destination is 32-bit data, two reads are performed,
then one 32-bit write.
• transfer_control_descriptor local memory
— memory controller: This logic implements the required dual-ported controller, handling
accesses from both the DMA engine as well as references from the IPS bus. As noted earlier,
in the event of simultaneous accesses, the DMA engine is given priority and the IPS transaction
is stalled. The hooks to a BIST controller for the local TCD memory are included in this
module.
— memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array
15.4.2 DMA basic data flow
The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 15-34, the first
segment involves the channel service request. In the diagram, this example uses the assertion of the
ipd_req[n] signal to request service for channel n. Channel service request via software and the TCDn.start
bit follows the same basic flow as an ipd_req. The ipd_req[n] input signal is registered internally and then
routed to through the DMA engine, first through the control module, then into the programming
model/channel arbitration (pmodel_charb) module. In the next cycle, the channel arbitration is performed,
either using the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated
channel number is sent through the address path (addr_path) and converted into the required address to
access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from
the local memory and loaded into the dma_engine.addr_path.channel_{x,y} registers. The TCD memory
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