NXP Semiconductors MPC5606S - DSPI POP RX FIFO Register (Dspix_Popr)

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 305
11.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR)
The DSPIx_POPR allows you to read the RX FIFO. Refer to Section 11.8.3.5, Receive First In First Out
(RX FIFO) buffering mechanism for a description of the RX FIFO operations. 8- or 16-bit read accesses
to the DSPIx_POPR fetch the RX FIFO data, and update the counter and pointer.
NOTE
Reading the RX FIFO field fetches data from the RX FIFO. Once the RX
FIFO is read, the read data pointer is moved to the next entry in the RX
FIFO. Therefore, read DSPIx_POPR only when you need the data. For
compatibility, configure the TLB (MMU table) entry for DSPIx_POPR as
guarded.
Table 11-15 describes the fields in the DSPI pop receive FIFO register.
11.7.2.8 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn)
The DSPIx_TXFRn registers provide visibility into the TX FIFO for debugging purposes. Each register is
an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the DSPIx_TXFRn
registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO:
DSPIx_TXFR0–DSPIx_TXFR3.
Address: Base + 0x0038 Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-8. DSPI POP RX FIFO Register (DSPIx_POPR)
Table 11-15. DSPIx_POPR field descriptions
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[0:15]
Received data. The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop
next data pointer (POPNXTPTR).