NXP Semiconductors MPC5606S - Qspi_Io2-Quadspi Data IO_2

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1001
driving one single SO line. The SO output line is High Impedance when in SPI Slave mode the QuadSPI
module is not selected by the SPI master.
In the Serial Flash mode it is used as I/O bit 1.
30.3.2.7 QSPI_IO2—QuadSPI Data IO_2
In Serial Flash mode this signal is used as I/O bit 2.
30.3.2.8 QSPI_IO3—QuadSPI Data IO_3
In Serial Flash mode this signal is used as I/O bit 3.
30.3.2.9 SCK — Serial Clock
SCK is a serial communication clock signal. In SPI Master mode, the QuadSPI generates the SCK from
the system clock.
In SPI Slave mode, SCK is an input from an external bus master.
In Serial Flash mode this signal is the serial clock output to the serial flash device and is based on the
auxiliary clock.
30.4 Memory map and register definition
30.4.1 IP bus register memory map
Table 30-6 shows the QuadSPI memory map.
Table 30-6. QuadSPI IP bus memory map
Address Register name
Global register for SPI modes and SFM mode
QSPI_BASE+0x000 Module Configuration Register (QSPI_MCR)
QSPI_BASE+0x004 Reserved
Registers valid in SPI modes only
1
QSPI_BASE+0x008 Transfer Count Register (QSPI_TCR)
QSPI_BASE+0x00C
–
QSPI_BASE+0x010
Clock and Transfer Attributes Registers 0 – 1 (QSPI_CTAR0 – QSPI_CTAR1)
QSPI_BASE+0x014
–
QSPI_BASE+0x028
Reserved
QSPI_BASE+0x02C SPI Status Register (QSPI_SPISR)
QSPI_BASE+0x030 SPI Interrupt and DMA Request Select and Enable Register (QSPI_SPIRSER)