Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1007
30.4.3.4 Clock and Transfer Attributes Registers 0 – 1
(QSPI_CTAR0
– QSPI_CTAR1)
The QSPI_CTAR registers are used to define different transfer attribute configurations for the SPI Master
mode and the SPI Slave mode. SPI transfers select which one of the QSPI_CTARs to get their transfer
attributes from. In the current implementation there are 2 different QSPI_CTARs selectable. The user must
not write to the QSPI_CTAR registers while the QuadSPI is in the Running state.
In Master mode, the QSPI_CTAR0–QSPI_CTAR7 registers define combinations of transfer attributes
such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave
mode, a subset of the bitfields in the QSPI_CTAR0 and QSPI_CTAR1 registers are used to set the slave
transfer attributes. See the individual bit descriptions for details on which bits are used in Slave modes.
When the QuadSPI is configured as a SPI Master, the CTAS field in the command portion of the TX FIFO
entry selects which of the QSPI_CTAR register is used. When the QuadSPI is configured as a SPI bus
Slave, the QSPI_CTAR0 register is used.
Table 30-10. QSPI_TCR field descriptions
Field Description
SPI_TCNT SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The
SPI_TCNT field counts the number of SPI transfers the QuadSPI makes. The SPI_TCNT field is
incremented every time the last bit of a SPI frame is transmitted. A value written to SPI_TCNT presets
the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT
field is set in the executing SPI Command. The Transfer Counter wraps around, i.e., incrementing the
counter past 0xFFFF resets the counter to zero.
Address: QSPI_BASE + 0x00C (QSPI_CTAR0)
QSPI_BASE + 0x010 (QSPI_CTAR1)
Write: Anytime
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DBR FMSZ
CPO
L
CPHA LSBFE PCSSCK PASC PDT PBR
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-4. Clock and Transfer Attributes Registers 0 – 1 (QSPI_CTAR0 – QSPI_CTAR1)
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