NXP Semiconductors MPC5606S - Main Status Register (MSR)

Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 145
5.4.2.2 Main Status Register (MSR)
The Main Status Register (MSR) provides status bits for the ADC.
24
ABORTCHAIN
Abort Chain
When this bit is set, the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon
as a new conversion is requested.
0 Conversion is not affected.
1 Aborts the ongoing chain conversion.
25
ABORT
Abort Conversion
When this bit is set, the ongoing conversion is aborted and a new conversion is invoked. This bit is
reset by hardware as soon as a new conversion is invoked.
0 Conversion is not affected.
1 Aborts the ongoing conversion.
Note: If the abort pulse is valid in the last cycle of the SAMPLE phase, the current channel is
correctly aborted but the data register (CDR[0..15]) of the next channel conversion shows
an invalid value.
26
ACKO
Auto-clock-off enable
If set, this bit enables the Auto clock off feature.
0 Auto clock off disabled.
1 Auto clock off enabled.
27–28 Reserved
Must be kept at 0.
29–30 Reserved
A write of any value has no effect. The read value is always 0.
31
PWDN
Power-down enable
When this bit is set, the analog module is requested to enter Power Down mode. When ADC status
is PWDN, resetting this bit starts ADC transition to Idle mode.
0 ADC is in normal mode.
1 ADC has been requested to power down.
Table 5-7. MCR field descriptions (continued)
Field Description